Fecha de publicación: 01/12/1992 Fuente: Wipo "digitalization" ABSTRACT A processor suitable for recursive computations incorporates multiplier cells (16) connected to form rows (12) and columns (14). Each row (12) is arranged to multiply by a coefficient. It begins with accumulator cells (18 and 20), and continues with multiplier cells (16) arranged to multiply by individual coefficient digits and disposed in descending order of digit significance. Columns (14) other than the first column (141 ) begin with a multiplier cell (16), and the higher significance columns (141 to 144) terminate at respective accumulator cells (20). Any intervening multiplier cells (16) are arranged in ascending order of multiplier digit significance. The multiplier and accumulator cells (16 to 20) operate in accordance with signed digit number representation arithmetic involving digit redundancy. They generate sum and transfer digits for output down columns (14) and along rows (12) respectively to neighbouring cells, in the direction of increasing digit significance in the case of transfer digits. The cell arithmetic employed makes it possible to compute results most significant digit first. Each result digit is recycled when formed to provide a multiplicand digit input for all multiplier cells (16) of a respective row (12) selected in accordance with result digit significance. The processor (10) is also arranged to add successive non-recursive input terms to multiplier products. This provides for the processor (10) to provide a first order infinite impulse response (IIR) filter section, and two cascaded processors (50,50') provide a second order IIR filter section.