Fecha de publicación: -- Fuente: Wipo "digitalization" 712,173. Automatic exchange systems. POSTMASTER GENERAL. Oct. 4, 1950 [Oct. 19, 1949], No. 26902/49. Class 40 (4) In a register-translator of the type described in Specification 657,058, the register includes pulse storing means in which pulses or groups of pulses representing digits are caused to circulate and be repeated, and in which further pulses applied to the storing means co-operate with the circulating pulses to effect switching operations. The circulating means employs a supersonic delay system, such as a column of mercury bounded at both ends by a quartz crystal. The principle of the delay circuit is illustrated by Figs. 1 (a), (b), (c). The register cycle of Fig. 1 (c) has ten equal cycle divisions P1-P10, each cycle division being started and ended respectively by short K1 or K2 pulses, Fig. 1 (b). An impulse applied over lead 11 to a valve trigger circuit 1, Fig. 1 (a), causes the emission of a register pulse, made up of a series of very short A.C. impulses, synchronized to fill the time between adjacent K1 and K2 pulses over lead 14, through a supersonic delay device 2 and amplifier 3 to apparatus 4, which receives K1 pulses and retransmits the synchronized register pulse to device 1, so that the register pulse when entered, continues to circulate with a period of one register cycle. Several pulses may be entered at different positions in the cycle. Registering digits.-In the register-translator shown' schematically in Figs. 4, 5 the storage system has a capacity for 200 register pulses each of 0.8 microsecs. duration, each cycle division lasting 1 microsecond. The cycle is divided into 40 sectors of 5 cycle divisions. According to each digit received over lead IN, apparatus 5 applies continuous signals to a selection of leads R1-5, and also sends a short signal over lead 51 and a shorter signal over lead 52. Pulses synchronized with cycle divisions P1-5 and P101-105 are applied to leads P1-5 and are communicated over those gates G1-5 which receive signals over leads R1-5. Hence device 45 receives a combination of pulses and transmits these pulses, while the signal on lead 52 lasts, into the delay circuit 2, 3, 4, 1. As an alternative, the P1-5 ,pulses may be timed 0.3 microseconds early, device 45 then feeding into device 4, as shown in a dotted line. Phase shift of registered digit.-When a digit has been registered as a combination of pulses in cycle divisions p1-5 and p101-105, its phase in the register cycle is shifted to p196-200 and p96-100 and the next digit is then registered. The normal delay circuit includes a delay line 73 having a delay of 5 microseconds, but to advance a recorded digit, a switch 6 is operated to replace line 73 by a no-delay lead 61 for one cycle. Devices 7561, 7533. re-synchronize the register pulses, the latter also feeding these pulses to a device 100, fed by lead P17 with pulses in cycle divisions. p196-200, i.e. the positions occupied by newly recorded pulses before passing through delay line 73. Coincidence of these signals operates device 101, to signal device 102, which then operates in response to a pulse at time p120 to operate device 6 and cause phase shift, device 102 being released at time p110 in the following cycle. Device 101 together with pulses from device 7531 and pulses at times P 116-120 on lead P16, also feeds device 103. 103 operates at coincidence of pulses, which occurs when a digit has been entered. at times p121-125, i.e. an indication that-recording is complete, and device 101 then releases to prevent further operation of device 6. Device 100, when operated by a signal over lead 51, disconnects 101 to prevent the shift taking place while a digit is being recorded. Translation.-The register circuit is connected to the translator circuit by a number of distributers, the arms D11, D12, D13 of which advance at a rate of one contact per register cycle, moving in a blank portion of the cycle. The translator impulses are received over leads PK65-100 and PK151-6