Fuente: Wipo "digitalization" 826,614. Electronic digital computers. NATIONAL RESEARCH DEVELOPMENT CORPORATION. Jan. 20, 1956 [Jan. 24, 1955], No. 2037/56. Divided out of 826,613. Class 106 (1). In an electronic digital computer " overflow " of an answer-representing number signal from the computing circuit (mill) beyond the range of numbers capable of being represented by the form of electric signals used, effects a control of the manner of subsequent operation of the machine dependent upon the form of order signal currently operative in the machine. For example, during a division operation, overflow causes an immediate stoppage of the machine, while during other operations overflow merely limits the manner of operation of the machine to prevent transfer of an erroneous answer arising from the overflow to a particular register. The invention is described as applied to the machine disclosed in Specifications 826,612 and 826,613 in which 42 digit-order-words, Fig. 2 (c), are each divided into A and B orders, each of which is similarly divided in time order into M, F, X, N digits. The three M digits define the address in the accumulator register group 2, Fig. 1, of the high speed store 10, of any required modifier word to be used for altering the subsequent N and/or X digits of the same order. The six F digits define the function to be performed by the machine. The three X digits select the particular accumulator register that is to be connected to the mill 5, and the seven N digits define the address in the store 10 (accumulator group 2 or a register group 4) where one operand is to be obtained or delivered. The normal operating cycle of the machine comprises A and B, periods during which the A, B orders respectively are obeyed, followed by a C period during which the next order word is selected and fed to the control line, Fig. 4. The A, B periods each have a length of two beats (D, E beats) but other beats may be interposed between the D, E beats dependent upon the order in question. The C period is of one beat length and each beat is of 42 digit intervals length. Of the seven accumulator registers 2, Fig. 1, the first five ACR1 ... ACR5, Fig. 6a, are as described in the abovementioned Specification 826,613. The " p " accumulator register ACR6, Fig. 6b, in addition to performing normal word storage like ACR1 ... ACR5 is also used for holding one of the operands in a multiplication or division operation in a single word storage register Q15. The accumulator ACR6 also includes a computing circuit AS1, and adding circuits ADR2, ADR3 provided with a regenerative loop of variable delay time between the output of adder ADR3 and the computing circuit input whereby a right or left shift of a number circulating in the circuit may be effected for each circulation. The " q " accumulator register ACR7, Fig. 6c, is also used for holding one of the operands during multiplication or division. The thirty-two address registers 4 and auxiliary registers 3, Fig. 6d (not shown) are as described in Specification 826,613. In addition to the beat counter and various staticisors described in that Specification, hand switches smO, sml ... sn9, Fig. 9, are provided for generating an order word. These switches are set according to the respective M, F, X, N digits of a desired order, and through " and " gates W10, W11 ... W31 controlled by clock pulses T0, T1 ... T20 pass a corresponding series mode signal over line Y13 to the control line, Fig. 4, the word being fed to line Y13 via the upper or lower gate of a doubleentry-gated-delay W37 to form an A or B order according to whether a switch MS is in its shown or reversed position. General operation.-A control address number signal is continuously circulating in the control number register A01, Fig. 4. This number is fed, during the E beat of the B period during which the immediately preceding order word is being obeyed, through a double entry-gated delay A21 to one input of the adder ADR1. At standard digit time 32 a single pulse i