Fuente: Wipo "digitalization" Two D flip-flops (D-FF MA , D-FF MB ) output two half-rate signals (D MR-A , D MR-B ) by dividing a digital input signal (D M ) into two signals and retiming them based on a clock signal (CLK) and a negative-phase clock signal (CLKB). First and second switches (S M1 , S M2 ) are driven by the two half-rate signals (D MR-A , D MR-B ). Third and fourth switches (S M3 , S M4 ) are driven by a select signal SW and a negative-phase select signal SWB that have the same frequency as that of the clock signal (CLK) but a different phase from that of the clock signal (CLK). The current supplied from a current source (1) to a load (4) thus becomes a current signal corresponding to a conversion frequency twice the frequency of the clock signal (CLK).