Fecha de publicación: 02/12/1970 Fuente: Wipo "digitalization" 1,214,168. Selective signalling. GIDDINGS & LEWIS Inc. 30 Jan., 1968 [27 Feb., 1967], No. 4616/68. Heading G4H. In a position digitizing system gear coupled resolvers 31a, 31b, 31c, 31d, Fig. 2a, each produce a phase significant signal which is squared, 61a, 61b, 61c, 61d, Fig. 2b, and used to gate 55a, 55b, 55c, 55d, the contents of a sweep generator counter 35 into fine, medium-fine, medium coarse, and coarse registers 53a, 53b, 53c, 53d. A similar group of resolvers is provided for each of three co-ordinate axes and the gating and registering circuits are time-shared. The registers 53a, 53b, 53c, 53d are arranged so that the highest denominational digit in any one is of the same denominational significance as the lowest denominational digit of the next. They are read out sequentially, lowest order digit first, into a compositor 83, which assumes that the contents of the fine register are correct and progressively modifies the higher order digits so as to produce a composite number indicating the desired position. An example of how the compositor functions is shown in Fig. 5a, in which a mediumfine (MF) reading of 88 has to be increased to 90 to bring its lowest significant digit into agreement with the highest significant fine digit, a medium coarse (MC) reading of 10 has to be reduced to 09, and a coarse (C) reading of 89 has to be increased to 90. Correction of any reading is effected in principle by stepping it either forwards or backwards so that its lowest digit assumes the required value after the least number of steps. Thus each reading has a tolerance of Œ4. The actual calculation, however, is effected by a complicated sequence of subtractions, additions and shifts using a sevenstage full-adder (201) and a shiftable accumulating register (205) (Fig. 4c, not shown) and, for the numbers given in Fig. 5a, is summarized in Table I. Two-phase resolvers 27a, Fig. 46, are energized by 500 c/s. sine and cosine waves obtained from a 2 Mc/s. clock. The clock also steps a binary coded decimal counter A, B, C, 102, at a frequency of 500 kc/s. so that each cycle of the resolver energizing potential is divided into 1,000. The phase significant output from the resolver rotor is squared, 57a, and its leading edge is reclocked, 71a, so that the contents of the counter ABC are gated into registers 53a at time when the count is steady. The counter ABC, together with a further decade D and binary-to-decimal converters 141, 143, 145 also produces control signals which cause operations to occur in the correct order. Thus, one complete cycle of operation of the system comprises 1000 programme times. From time 001 to time 120 the output of the x-axis resolvers is examined-see gate 63a, Fig. 46. Actually 100 programmes times corresponds to one cycle of the resolver energizing potentials, but since the rotor may be moving when its output is examined 120 programme times are allowed because the frequency of the resolver output may fall below 500 c/s.