Fecha de publicación: 29/08/2024 Fuente: WIPO "varroa" A memory device is provided. The memory device includes: a latch circuit, having a first inverter and a second inverter cross-coupled with each other, wherein a first pull up transistor and a first pull down transistor of the first inverter are coupled through a first selection transistor, and a second pull up transistor and a second pull down transistor of the second inverter are coupled through a second selection transistor; a first access transistor, coupled to a first storage node of the latch circuit; and a second access transistor, coupled to a second storage node of the latch circuit.